This patent application claims priority based on Japanese patent applications, H10-319637 filed on Nov. 10, 1998, and H11-310748 filed on Nov. 1, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a test device, a test pattern generator for generating test patterns and a method of generating a plurality of test patterns for testing an electrical device.
2. Description of the Related Art
A conventional test pattern generator of a testing device for an electrical device comprises a SRAM or a DRAM having a large capacity to store programs for generating test patterns. The DRAM is used when the capacity of the SRAM is not enough to store necessary programs to generate the test patterns. When the DRAM is used, a test pattern is generated from the DRAM via a cache memory, because the DRAM needs to be refreshed at a predetermined period and there is inconvenient when an address of a different ROW is accessed in using the DRAM.
FIG. 1 is a block diagram of a conventional test pattern generator comprising an SRAM. The conventional test pattern generator comprises a sequence controller 62 and a pattern signal generator 26. The sequence controller 62 comprises a vector memory 12, vector memory banks 16 and 18, a vector instruction multiplexer 20 and an address expander 22. The pattern signal generator 26 comprises a pattern memory using the SRAM. The sequence controller 62 generates address signal 24 in a desired order. When the address signal 24 is successively input to the pattern signal generator 26, each of the memory addresses stored in the pattern signal generator 26 are linked with each of the test patterns, to produce a desired series of test patterns. Thus the test patterns are generated.
The read out controller 14 of the sequence controller 62 reads out the vector instructions stored in the vector memory 12. The vector instructions are temporarily stored in the vector memory banks 16 and 18. The vector instruction multiplexer 20 selects a vector instruction from among the vector instructions temporarily stored in the vector memory banks 16 and 18, and outputs the selected vector instruction to the address expander 22. The address of the address signal 24 is expanded by the address expander 22 and transferred to the pattern signal generator 26. Each of the pattern signals stored in the pattern memory is linked with each of the address signal 24 in the pattern signal generator 26 to generate test pattern signals 28 for testing an electrical device.
FIG. 2 shows an example of a pattern program to be stored in the vector memory 12. The instruction xe2x80x9cGOSUB Axe2x80x9d means that the routine should go to the sub routine labeled xe2x80x9cAxe2x80x9d. The instruction xe2x80x9cRETURNxe2x80x9d means that the sub routine should be terminated and the routine should return to the next instruction (at an address one address added to the previous address) of the instruction xe2x80x9cGOSUBxe2x80x9d. The instruction xe2x80x9cREPEAT nxe2x80x9d means that the test pattern of the indicated address should be output n times. The instruction xe2x80x9cNEXTxe2x80x9d means that the routine should go to the next address (one address added to the previous address). The instruction xe2x80x9cSTOPxe2x80x9d means that the test should be terminated.
The test patterns for an electrical device are generated by arranging each of the individual test patterns determined by these vector instructions. The instructions of the addresses #11 to address #15 are labeled xe2x80x9cAxe2x80x9d, and function as the sub routines.
FIG. 3 shows an example of a compressed pattern program to be stored in the vector memory. The pattern program of the vector instructions shown in FIG. 2 comprises the instructions xe2x80x9cNEXTxe2x80x9d which means that the routine should go to the next address. Therefore, the instructions xe2x80x9cNEXTxe2x80x9d are omitted and the pattern program is compressed, as show in FIG. 3, to be stored in the vector memory. In this application, the instructions xe2x80x9cNEXTxe2x80x9d are omitted and the pattern program is compressed as a whole. The result is that a small capacity vector memory can serve as the test pattern generator.
The instruction xe2x80x9cGOSUB A #0 #11xe2x80x9d means that the instruction of the address #0 is xe2x80x9cGOSUB Axe2x80x9d and the address to which the routine should go is #11. The instruction xe2x80x9cREPEAT 3 #3xe2x80x9d means that the instruction of the address #3 is xe2x80x9cREPEAT 3xe2x80x9d, so the instruction of the address #3 should be repeated three times. This also means that the instructions of the address #1 and the address #2 are xe2x80x9cNEXTxe2x80x9d. Thus, the pattern program is compressed as a whole.
FIG. 4 shows instructions to be stored in the pattern signal generator 26. Predetermined patterns shown as PAT0, PAT1, . . . , PATn are previously stored in an external storage device such as a hard disk, not shown in the drawings. The predetermined patterns are then read out from the hard disk when the device is switched on, and stored in the respective addresses #0, #1, . . . , #n of the pattern signal generator 26.
FIG. 5 shows the operation of a conventional test pattern generator. In FIG. 5, each of the vector memory banks 16 and 18 store three words. The pattern generator 60 is initialized before the test is started. At the initialization, the vector instructions are read out from the vector memory 12 having been previously stored in the vector memory bank 16, based on the instructions from the read out controller 14 shown in FIG. 1.
The read out controller 14 shown in FIG. 1 outputs the instructions stored in the vector memory 12 to the vector memory bank 16, taking the sequences into consideration. For example, the instruction xe2x80x9cGOSUB Axe2x80x9d means that the routine should go to the sub routine labeled xe2x80x9cAxe2x80x9d, therefore the instruction xe2x80x9cREPEAT 2 #13xe2x80x9d is written next to the instruction xe2x80x9cGOSUB A #0 #11xe2x80x9d.
When the instruction xe2x80x9cRPEATxe2x80x9d is output, the routine goes to the next address. The instruction xe2x80x9cRETURN #15 #1xe2x80x9d is written next to the instruction xe2x80x9cREPEATxe2x80x9d. The initialization is completed when the first three words are written in the vector memory bank 16. The test is started when the initialization of the test pattern generator 60 is completed. The test proceeds as explained in the following. The address expander 14 shown in FIG. 1 expands the compressed instructions that were stored in the vector memory bank 16, while the test pattern generator 60 is initialized.
The address signal 24 comprising the pattern memory using SRAM is supplied to the pattern former 26. The pattern former 26 outputs the test patterns stored therein based on the address signal 24 and applies the output test pattern signals to the electrical device 76. After the test is started, the vector instruction multiplexer 20 selectively outputs to the address expander 22 the compressed instructions from the vector memory banks in which the vector instructions were previously stored,
A program comprising the three words stored in the vector memory bank 16 executes the instructions shown below at the initialization. Firstly, the routine goes to the address #11 from the address #0 by the instruction xe2x80x9cGOSUB A #0, #11xe2x80x9d. The routine then goes from the address #11 to the address #13 in order, and the address #13 is repeated twice by the instruction xe2x80x9cREPEAT 2 #13xe2x80x9d. The routine then proceeds to the address #14. The routine proceeds from the address #14 to the address #15, and goes to the address #1 by the instruction xe2x80x9cRETURN #15 #1xe2x80x9d.
While the test patterns are generated by the vector memory bank 16, the vector instruction to be executed next is transferred from the vector memory 12 to the vector memory bank 18 based on the instructions from the read out controller 14. After the test patterns are generated by the vector memory bank 16, another series of test patterns are generated based on the instructions stored in the vector memory bank 18. While the test patterns are generated by the vector memory bank 18, the vector instruction to be executed next is transferred from the vector memory 12 to the vector memory bank 16, based on the instructions from the read out controller 14. Similarly, another series of test patterns are generated based on the instructions stored in the vector memory bank 16 after the test patterns are generated by the vector memory bank 18.
By repeating these operations, the test patterns are successively output from either of the vector memory banks 16 and 18. The conventional test pattern generator minimizes the pattern program by using the initialize pattern including sub routine such as the instruction xe2x80x9cGOSUBxe2x80x9d and the xe2x80x9clabel Axe2x80x9d in common. By minimizing the pattern program, the required capacity of the vector memory 12 is minimized.
FIG. 6 shows a block diagram of the conventional pattern former 26 comprising a DRAM. The pattern former 26 comprises a pattern memory 32 composed of the DRAM, a transfer controller 34, multiplexers 36 and 38 for the pattern memory, cache memory banks 40 and 42 for the pattern memory, and a multiplexer 44 for the pattern cache memories.
The pattern former 26 comprising the DRAM generates the test pattern signals from the pattern memory 32 via the cache memories 40 and 42. The operation of the pattern former 26 will be explained in the following. The address signal 24 is transferred to the multiplexers 36 and 38, and the transfer controller 34. When the address signal 24 is input to the multiplexer 44, the multiplexer 44 selects either of the cache memory banks 40 and 42 based on the difference of the former bit and reads out the pattern signals from the selected cache memory bank.
The address signal 24 is also input to the multiplexers 36 and 38, and the transfer controller 34. The transfer controller 34 selects either of the pattern memory banks 40 and 42 from which the pattern signal is then completely read out based on the bits indicating the address. The transfer controller then transfers the next pattern signals from the pattern memory 32 to the selected pattern memory bank 40 or 42 via the multiplexer 44 connected to the selected pattern memory bank 40 or 42. When the address signal is input to the transfer controller 34, the test patterns are selectively transferred to either of the pattern memory banks 40 or 42. The desired test patterns are generated by the multiplexer 44 based on the address information.
When the SRAM is used as the pattern memory of the pattern signal generator 26, the required capacity of the pattern memory is minimized using a sub routine. However, with large scale electrical devices and multifunctional electrical devices, the number of test patterns necessary for testing a single electrical device is increasing. The capacity of the SRAM is not large enough to store these numbers of patterns required. Thus it is required to use a DRAM for the test pattern generator.
FIG. 7 shows a pattern program including the initialize pattern at the start of each test lists. Only successive addresses can be transferred to the cache memory from the DRAM. In the case when only the successive addresses are transferred to the cache memory, it is impossible to include a sub routine. Therefore, in this case, the initialize pattern of each of the test lists is written at the start of each test list without including the sub routine. The result is that a DRAM having an extremely large capacity is required because the DRAM needs to store the initialize pattern for each of the test lists.
Therefore, it is an object of the present invention to provide a test pattern generator, a memory testing device, and a method of generating a plurality of test patterns which overcome the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to solve the above-stated problem, the present invention provides a test pattern generator for generating a test pattern for testing electrical characteristics of an electrical device comprising: a pattern memory for storing the test pattern; a pattern cache memory for storing the test pattern read out from the pattern memory; a vector memory for storing a vector instruction indicating an order of the test pattern to be generated; a read out controller for judging whether an address of the test pattern to be read out from the pattern memory is to be jumped or not based on the vector instruction read out from the vector memory; and a transfer controller for reading out the test pattern from the jumped address, and for transferring the jumped address to a pattern cache memory when the read out controller judges the address is to be jumped.
The test pattern may comprise a main test pattern and a sub test pattern which is repeatedly incorporated in the main test pattern. The pattern cache memory may comprise a main test pattern cache memory for storing the main test pattern read out from the pattern memory and a sub test pattern cache memory for storing the sub test pattern read out from the pattern memory.
The read out controller may comprise means for detecting an instruction to read out the sub test pattern. The transfer controller may comprise means for transferring the sub test pattern from the pattern memory to the sub test pattern cache memory when the read out controller detects the instruction to read out the sub test pattern.
In order to solve the above-stated problem, the present invention further provides a test pattern generator for generating a test pattern for testing electrical characteristic of an electrical device, the test pattern comprising a main test pattern and a sub test pattern which is repeatedly incorporated in the main test pattern, comprising: a pattern memory for storing the main test pattern and the sub test pattern; a main test pattern cache memory for storing the main test pattern read out from the pattern memory; and a sub test pattern cache memory for storing the sub test pattern read out from the pattern memory.
The main test pattern cache memory may comprise two pattern memory banks. The test pattern generator may further comprise a main test pattern multiplexer for reading out the main test pattern previously stored in one of the pattern memory banks to provide the read out main test pattern to the electrical device while the main test pattern read out from the pattern memory is being transferred to the other of the pattern memory banks.
The sub test pattern cache memory may comprise two pattern memory banks. The test pattern generator may further comprise a sub test pattern multiplexer for reading out the sub test pattern previously stored in one of the pattern memory banks to provide the read out sub test pattern to the electrical device while the sub test pattern read out from the pattern memory is being transferred to the other of the pattern memory banks.
The test pattern generator may further comprise: a vector memory for storing a vector instruction indicating an order of the test pattern to be generated; a read out controller for previously detecting that the sub test pattern is to be generated based on the vector instruction read out from the vector memory; and a transfer controller for transferring the sub test pattern from the pattern memory to the sub test pattern cache memory in a case when the read out controller detects that the sub test pattern is to be generated.
The test pattern generator may further comprise a vector cache memory for storing the vector instruction readout from the vector memory. The read out controller may detect that the sub test pattern is to be generated at a time when the vector instruction read out from the vector memory is being transferred to the vector cache memory.
The test pattern generator may further comprise an address expander generating an address of the test pattern to be read out from the pattern memory based on the vector instruction read out from the vector cache memory.
The vector cache memory may comprise three vector memory banks. The pattern generator may further comprise a vector instruction multiplexer for providing the vector instruction read out from one of the three vector memory banks to the address expander while the vector instruction is written on another one of the vector memory banks.
The read out controller may further comprise means for detecting an end address of the sub test pattern. The transfer controller may transfer a new sub test pattern to be read out, which was detected by the read out controller after the sub test pattern of the end address detected by the read out controller is transferred, to the sub test pattern cache memory.
The sub test pattern cache memory may comprise: a ring buffer capable of outputting the sub test pattern with successively updating the sub test pattern therein; and a fixed buffer capable of outputting the sub test pattern with storing the sub test pattern therein.
The vector instructions may comprise a main routine for reading out the main test pattern from the pattern memory and a sub routine for reading out the sub test pattern from the pattern memory. The transfer controller may store a first part of the sub test pattern successively read out from the pattern memory by the sub routine. The sub test pattern, which is read out by the sub routine from the pattern memory and which is not stored in the fixed buffer, may be successively stored in the ring buffer and output from the ring buffer when the sub routine is executed.
The read out controller may further comprise an information detector for detecting an information of the sub routine stored in the vector memory. The transfer controller may store the sub test pattern in either of the fixed buffer and/or the ring buffer based on the information of the sub routine.
The information detector may detect a start address of the sub routine and stores the sub test pattern read out by a first part of the sub routine from the pattern memory based on the start address.
The information detector may comprise a sub routine number detector for detecting a number of the sub routine stored in the vector memory. The transfer controller may have the fixed buffer store the sub test pattern read out by each of the sub routine of the plurality of the sub routine, when a plurality of sub routine is included.
The sub routine number detector may comprise: a return instruction detector detecting a number of return instructions included in the vector instruction, and a sub routine number storage counting a number of the return instructions.
The sub routine number detector may comprise: a jump instruction detector for detecting a jump instruction included in the vector instruction, a judging unit for judging whether an address appointed by the jump instruction is previously appointed by the jump instruction as a jumped address, and a sub routine number storage for counting a number that the judging unit judges that the address appointed by the jump instruction was not previously appointed as the jumped address.
The judging unit may comprise: a register for storing the address which is judged not to be previously appointed as the jumped address, and an identical detector for detecting when the jump instruction detector detects the jump instruction, whether or not the address stored in the register and an address appointed by the jump instruction are same.
The information detector may comprise a capacity detector for detecting a capacity of the sub test pattern. The test pattern generator may store, when the capacity of the sub test pattern is smaller than a capacity of the sub test pattern cache memory, the sub test pattern in the ring buffer by assuming the ring buffer as a second fixed buffer.
The capacity detector may comprise: a start address detector for detecting a start address of the sub test pattern which is read out by the sub routine at first, and an end address detector for detecting an end address of the sub test pattern which is read out by the sub routine at last. The capacity detector may detects: the capacity of the test pattern by subtracting the start address of the test pattern read out at first from the end address of the test pattern read out at last.
The information detector may detect an information of the sub routine at a time when the vector instruction is being stored in the vector memory.
The fixed buffer may store the sub test pattern in a manner such that a time required to store the sub test pattern stored in the pattern memory to the ring buffer is longer than a time required to output the sub test pattern stored in the fixed buffer.
In order to solve the above-stated problem, the present invention further provides a test pattern generator for outputting a test pattern for testing an electrical device based on a vector instruction including a main routine and a sub routine comprising: a main test pattern cache memory previously provided as an area for storing a main test pattern output based on the main routine; a sub test pattern cache memory previously provided as an area for storing a sub test pattern output based on the sub routine; and outputting: the test pattern stored in the main test pattern cache memory and the sub test pattern cache memory.
The test pattern generator may comprise a read out controller for detecting the sub routine included in the vector instruction, and a transfer controller for having the sub test pattern cache memory store the sub test pattern when the sub routine is detected.
In order to solve the above-stated problem, the present invention further provides a test device for testing electrical characteristics of an electrical device by using a test pattern comprising: a pattern memory for storing a test pattern including an input test pattern to be applied to the electrical device for the test and an expected value pattern output from an normal electrical device when the input test pattern is applied to the normal electrical device; a pattern cache memory for storing the test pattern read out from the pattern memory; a vector memory for storing a vector instruction indicating an order of the test pattern to be generated; a read out controller for judging whether an address of the test pattern to be read out from the pattern memory is to be jumped or not based on the vector instruction read out from the vector memory; a transfer controller for reading out the test pattern from the jumped address and for transferring the jumped address to the pattern cache memory when the read out controller judges the address is to be jumped; a pin data selector for reallocating a physical allocation of at least a signal composing the test pattern read out from the pattern cache memory in accordance with arrangements of electrical terminals of the electrical device; a waveform generator for generating a waveform of the input test pattern included in the test pattern output from the pin data selector; a device acceptor for accepting the electrical device and applying the input test pattern generated by the waveform generator to the electrical device; and a comparing unit for comparing an output signal output from the electrical device by applying the input test pattern and the expected value pattern.
In order to solve the above-stated problem, the present invention provides a test device for testing electrical characteristic of an electrical device by using a test pattern, the test pattern comprising a main test pattern and a sub test pattern which is repeatedly incorporated in the main test pattern, each of the main test pattern and the sub test pattern respectively comprising an input test pattern to be applied to the electrical device for the test and an expected value pattern output from a normal electrical device when the input test pattern is applied to the normal electrical device, comprising: a pattern memory for storing the main test pattern and the sub test pattern; a main test pattern cache memory for storing the main test pattern read out from the pattern memory; a sub test pattern cache memory for storing the sub test pattern read out from the pattern memory; a multiplexer for selecting either of the main test pattern read out from the main test pattern cache memory and the sub test pattern read out from the sub test pattern cache memory; a pin data selector for reallocating a physical allocation of at least a signal composing the test pattern selected by the multiplexer in accordance with arrangements of electrical terminals of the electrical device; a waveform generator for generating a waveform of the input test pattern included in the test pattern output from the pin data selector; a device acceptor for accepting the electrical device and applying the input test pattern generated by the waveform generator to the electrical device; and a comparing unit for comparing an output signal output from the electrical device by applying the input test pattern and the expected value pattern.
In order to solve the above-stated problem, the present invention provides a test device for testing electrical characteristics of an electrical device by using a test pattern, the test pattern being generated based on a vector instruction including a main routine and a sub routine, the test pattern comprising a main test pattern and a sub test pattern which is repeatedly incorporated in the main test pattern, each of the main test pattern and the sub test pattern respectively comprising an input test pattern to be applied to the electrical device for the test and an expected value pattern output from a normal electrical device when the input test pattern is applied to the normal electrical device, comprising: a test pattern generator for storing a main test pattern appointed by the main routine in and outputting the stored main pattern from a memory previously provided for main routine and for storing a sub test pattern appointed by the sub routine in and outputting the stored main pattern from a memory previously provided for sub routine; a multiplexer selecting either of the main test pattern read out from the memory provided for the main routine, and the sub test pattern read out from the memory provided for the sub routine; a pin data selector for reallocating a physical allocation of at least a signal composing the test pattern selected by the multiplexer in accordance with arrangements of electrical terminals of the electrical device; a waveform generator for generating a waveform of the input test pattern included in the test pattern output from the pin data selector; a device acceptor for accepting the electrical device and applying the input test pattern generated by the waveform generator to the electrical device; and a comparing unit for comparing an output signal output from the electrical device by applying the input test pattern and the expected value pattern.
In order to solve the above-stated problem, the present invention provides a method of generating a test pattern for electrically testing an electrical device comprising: a reading out step of reading out a vector instruction indicating an order of the test pattern to be generated from a vector memory storing the vector instruction; a judging step of judging whether an address of the test pattern to be read out from the pattern memory is to be jumped or not based on the vector instruction read out from the vector memory; and a transferring step of reading out the test pattern from the jumped address and transferring the jumped address to a pattern cache memory when the read out controller judges the address is to be jumped.
The test pattern may comprise a main test pattern and a sub test pattern which is repeatedly incorporated in the main test pattern. The judging step may judge whether the sub test pattern is read out or not. The transferring step may comprise steps of: storing the main test pattern read out from the pattern memory in a main test pattern cache memory provided in the pattern cache memory; and storing the sub test pattern read out from the pattern memory in a sub test pattern cache memory provided in the pattern cache memory.
The judging step may comprise a step of detecting an instruction to read out the sub test pattern. The transferring step may transfer the sub test pattern from the pattern memory to the sub test pattern cache memory when the instruction to read out the sub test pattern is detected in the judging step.
In order to solve the above-stated problem, the present invention further provides a method of generating a test pattern for electrically testing an electrical device, the test pattern comprising a main test pattern and a sub test pattern which is repeatedly incorporated in the main test pattern comprising steps of: reading out the main test pattern from a pattern memory storing the main test pattern and the sub test pattern and transferring the main test pattern to a main test pattern cache memory; and reading out the sub test pattern from the pattern memory and transferring the sub test pattern to a sub test pattern cache memory.
The main test pattern cache memory may comprise two pattern memory banks. The method of generating a test pattern may further comprise a step of reading out the main test pattern previously stored in one of the pattern memory banks to provide the read out main test pattern to the electrical device while the main test pattern read out from the pattern memory is being transferred to the other of the pattern memory banks.
The sub test pattern cache memory may comprise two pattern memory banks. The method of generating a test pattern may further comprise a step of reading out the sub test pattern previously stored in one of the pattern memory banks to provide the read out sub test pattern to the electrical device while the sub test pattern read out from the pattern memory is being transferred to the other of the pattern memory banks.
The method of generating a test pattern may further comprise: a reading out step of reading out a vector instruction indicating an order of the test pattern to be generated from a vector memory storing the vector instruction; a detecting step of previously detecting that the sub test pattern is to be generated based on the read out vector instruction; and a transferring step of transferring the sub test pattern from the pattern memory to the sub test pattern cache memory in case when the sub test pattern is detected to be generated.
The method of generating a test pattern may further comprise a step of storing the vector instructions read out from the vector memory in the reading out step in a vector cache memory.
The method of generating a test pattern may further comprise an address generating step of generating an address of the test pattern to be read out from the pattern memory based on the vector instruction read out from the vector cache memory.
The vector cache memory may comprise three vector memory banks. The address may be generated by the vector instruction read out from one of the vector memory banks while the vector instruction being written on another one of the vector memory banks in the address generating step.
The method of generating a test pattern may further comprise a detecting step of detecting an end address of the sub test pattern, wherein the transferring step transfers a new sub test pattern from the pattern memory to the sub test pattern cache memory when the new sub test pattern detected to be read out in the detecting step after the sub test pattern of the end address is transferred.
The sub test pattern cache memory may comprise: a ring buffer capable of outputting the sub test pattern with successively updating the sub test pattern therein; and a fixed buffer capable of outputting the sub test pattern with storing the sub test pattern therein. The vector instructions may comprise a main routine for reading out the main test pattern from the pattern memory and a sub routine for reading out the sub test pattern from the pattern memory. The step for storing in the sub test pattern cache memory may comprise: a step of storing a first part of the sub test pattern successively read out from the pattern memory by the sub routine in the fixed buffer, and,a step of successively storing the sub test pattern, which is read out by the sub routine from the pattern memory and which is not stored in the fixed buffer in the ring buffer.
In order to solve the above-stated problem, the present invention provides a cache device for temporarily storing a group of data stored in a data storing unit and outputting the group or data comprising: a fixed buffer temporarily storing a part of data included in the group of data; a ring buffer for successively updating a part of data other than the part of data stored in the fixed buffer and included in the group of data and outputting the group of data; and a transfer controller for having the fixed buffer store a first part of the group of data and having the ring buffer store a part of data other than the first part of the group of data; wherein the fixed buffer and the ring buffer output the stored data.
The data storing unit may comprise a first group of data and a second group of data. The transfer controller may have the fixed buffer store a first part of each of the first group of data and the second group of data.
The data to be stored in the fixed buffer and /or the ring buffer may be read out from the data storing unit in a same order as an order of the data to be output from the cache device.